1) Field of the Invention
The present invention relates to an apparatus and a method for controlling an address conversion buffer, such that a processor can execute a plurality of threads simultaneously on one core without increasing a capacity of the address conversion buffer.
2) Description of the Related Art
Computer systems adopting a virtual storage method use a conversion table known as a page table, to convert a virtual address into a physical address. The page table is normally stored in a main memory, but because the speed of accessing the main memory is low with respect to an operation of a CPU (Central Processing Unit). Therefore, if the page table in the main memory is referred to for every address conversion, the performance of the systems deteriorates.
Japanese Patent Application Laid-open Publication No. H6-259329 discloses a method in which an address conversion buffer called Translation Lookaside Buffer (TLB) is provided in the CPU, and a history of address conversion is cached therein, so that the access to the page table in the main memory is reduced as much as possible.
In recent years, the capacity of TLB has increased with an increase in an address space used by programs. This is because the small capacity of TLB causes many TLB malfunctions, and thus the performance of the systems deteriorates. Although a CPU adopting a multi-thread architecture that can execute a plurality of threads simultaneously on one processor core has been generally used, it is necessary to retain the history of the address conversion for the threads in the CPU compatible with the multi-threading. Hence, the necessary capacity of TLB further increases.
However, to increase the capacity of the TLB, the packaging area of the TLB must be large, and this causes difficulty in CPU production, and the cost increases. Particularly in CPUs adopting the multithread architecture, resources cannot be shared among threads, and thus, it is difficult to allocate a large packaging area to the TLB.